1. Field of the Invention
The present invention relates to a semiconductor memory device and a semiconductor device having the same. More specifically, the invention relates to a nonvolatile ferroelectric random access memory using a ferroelectric capacitor (referred to as a FeRAM hereinafter) and a FeRAM-embedded large-scale integrated circuit (referred to as an LSI hereinafter).
2. Description of the Related Art
Attention has recently been attracted to a FeRAM as a semiconductor memory device. Refer to Jpn. Pat. Appln. KOKAI Publication No. 2002-175697, for example.
FIG. 1 shows an example of a configuration (a 1T-1C configuration) of a memory cell MC of a FeRAM. Referring to FIG. 1, the memory cell MC includes a ferroelectric capacitor (C) 101 and a metal oxide semiconductor (MOS) transistor (T) 102 that are connected in series. More specifically, the gate, drain, and source of the MOS transistor 102 are connected to a word line WL, a bit line BL, and one electrode (upper electrode) of the ferroelectric capacitor 101, respectively. The other electrode (lower electrode) of the ferroelectric capacitor 101 is connected to a plate line PL.
The memory cell MC stores data using hysteresis properties of a ferroelectric, as shown in FIG. 2. When the voltage of the ferroelectric capacitor 101 is 0V, the remanent polarization (amount) P of the ferroelectric on the positive side represents “1” and that of the ferroelectric on the negative side represents “0.” Thus, the memory cell MC stores data.
There follows an explanation of an operation of writing/reading data to/from the FeRAM. This operation is carried out by applying a given pulse to the plate line PL.
First, the principle of the FeRAM in write operation will be described using a memory cell MC having a 2T-2C configuration shown in FIG. 3. Basically, the same is true of the principle of a memory cell MC having a 1T-1C configuration shown in FIG. 1. FIG. 4 depicts a timing pulse that is generated in write operation.
In the 2T-2C memory cell MC shown in FIG. 3, remanent polarizations P whose directions are opposite to each other are written to ferroelectric capacitors 101a and 101b that are connected to paired bit lines BLa and BLb via MOS transistors 102a and 102b, respectively. For example, the potential of the bit line BLa is set at the ground level (0V) and that of the bit line BLb is set at 5V. If, in this case, the potential of the word line WL is 6V or higher (but the power supply voltage Vcc is 5V and the threshold voltage VTH of each of the transistors 102a and 102b is 1V), the potential of the upper electrode of the ferroelectric capacitor 101a is 0V and that of the upper electrode of the ferroelectric capacitor 101b is 5V.
After the word line WL is set at a high potential (high level), a pulse PW as shown in FIG. 4 is applied to the plate line PL. For example, 0V is applied to the plate line PL at timing T1 (see FIG. 5B), 5V is applied thereto at timing T2 (see FIG. 6B), and 0V is applied thereto at timing T3 (see FIG. 7B). In FIGS. 5B, 6B and 7B, each of the arrows indicates the direction of remanent polarization P.
At timing T1, the remanent polarization P of the ferroelectric capacitor 101a is located at a remanent polarization point A (FIG. 5A), and that of the ferroelectric capacitor 101b is located at a remanent polarization point D (FIG. SC). At timing T2, the remanent polarization P of the ferroelectric capacitor 101a moves from the remanent polarization point A to a remanent polarization point B (FIG. 6A), and that of the ferroelectric capacitor 101b moves from the remanent polarization point D to a remanent polarization point E (FIG. 6C). At timing T3, the remanent polarization P of the ferroelectric capacitor 101a moves from the remanent polarization point B to a remanent polarization point C (FIG. 7A), and that of the ferroelectric capacitor 101b moves from the remanent polarization point E to the remanent polarization point D (FIG. 7C). Thus, the data write operation is completed. If this operation is defined as writing of data “0,” writing of data “1” is defined as follows: the remanent polarization P located at the remanent polarization point D is written to the ferroelectric capacitor 101a, and the remanent polarization P located at the remanent polarization point C is written to the ferroelectric capacitor 101b. 
Assume that power is shut down and the external electric field applied to the plate line PL and bit lines BLa and BLb becomes 0V. In this case, too, when data “0” is written, charges +Pr located at the remanent polarization point C are stored in the ferroelectric capacitor 101a, and charges −Pr located at the remanent polarization point E are stored in the ferroelectric capacitor 101b. Conversely, when data “1” is written, charges −Pr located at the remanent polarization point E are stored in the ferroelectric capacitor 101a, and charges +Pr located at the remanent polarization point C are stored in the ferroelectric capacitor 101b. 
On the other hand, reading of data from the FeRAM is usually a destructive read. A rewrite operation is therefore required even in read operation and after all the read operation is almost the same as the write operation.
FIG. 8 illustrates a data read operation taking the above 2T-2C memory cell MC as an example. FIG. 9 shows a timing pulse generated in read operation.
In order to read data, as shown in FIG. 8, the potentials of the bit lines BLa and BLb are set at the ground level (0V) in the first precharge cycle. A sense amplifier (not shown) is separated from each of the bit lines BLa and BLb and. Under these conditions, the potential of the word line WL is set at 6V or higher. Thus, the potentials of the upper electrodes of the ferroelectric capacitors 101a and 101b both become 0V. In FIG. 8, the arrows indicate the directions of remanent polarizations P.
In read operation, a pulse PR as shown in FIG. 9 is applied to the plate line PL, as in the write operation described above. For example, 0V is applied to the plate line PL at timing T1 (FIG. 10B), 5V is applied thereto at timing T2 (FIG. 11B), and 0V is applied thereto at timing T3 (FIG. 12B). In FIGS. 10B, 11B and 12B, the arrows indicate the directions of remanent polarizations P.
Assume that the remanent polarizations P as shown in FIGS. 10A and 10C are written to the ferroelectric capacitors 101a and 101b by writing data “0.” More specifically, assume that the remanent polarization P of the ferroelectric capacitor 101a is written to the remanent polarization point C and that of the ferroelectric capacitor 101b is written to the remanent polarization point E at timing T1. If data “0” is read in this case, the potential of the plate line PL changes from 0V to 5V at timing T2. Thus, the remanent polarization P of the ferroelectric capacitor 101a moves from the remanent polarization point C to the remanent polarization point B (see FIG. 11A), and that of the ferroelectric capacitor 101b moves from the remanent polarization point E to the remanent polarization point B (see FIG. 11C). Data of the ferroelectric capacitor 101b, the direction of remanent polarization P of which is inverted, is destroyed temporarily.
If data “1” is read, the remanent polarization P of the ferroelectric capacitor 101a moves from the remanent polarization point E to the remanent polarization point B and that of the ferroelectric capacitor 101b moves from the remanent polarization point C to the remanent polarization point B at timing T2. Data of the ferroelectric capacitor 101a, the direction of remanent polarization P of which is inverted, is destroyed temporarily.
The potential of the bit line connected to the ferroelectric capacitor the direction of remanent polarization P of which is inverted is slightly higher than that of the bit line connected to the ferroelectric capacitor the direction of remanent polarization P of which is not inverted. Data “0” or “1” can thus be read by sensing a difference in potential between the bit lines BLa and BLb. When data “0” is read, the potential of the bit line BLa becomes 0V and that of the bit line BLb becomes 5V. When data “1” is read, the potential of the bit line BLa becomes 5V and that of the bit line BLb becomes 0V.
The data that is destroyed by polarization inversion is rewritten to a memory cell MC within the same read cycle as the potential of the plate line PL changes from 5V to 0V. More specifically, when data “0” is read, the remanent polarization P of the ferroelectric capacitor 101a moves from the remanent polarization point B to the remanent polarization point C (FIG. 12A) and that of the ferroelectric capacitor 101b moves from the remanent polarization point C to the remanent polarization point D at timing T3 (FIG. 12C). When data “1” is read, the remanent polarization P of the ferroelectric capacitor 101a moves from the remanent polarization point C to the remanent polarization point D and that of the ferroelectric capacitor 101b moves from the remanent polarization point B to the remanent polarization point C at timing T3. The read operation is completed accordingly.
An FeRAM whose memory cells have a 1T-1C configuration requires a dummy cell that generates a reference potential to sense a small variation (potential difference) of bit lines or data “0” or “1.”
FIG. 13 shows a basic configuration of a prior art FeRAM. In the FeRAM, a sense amplifier 111 reads data out of a cell area (array) 112. This data is rewritten to the cell area 112 in read operation as described above.
The FeRAM causes a so-called imprint phenomenon. The imprint phenomenon is as follows. If a cell is left unattended with data written thereto, its hysteresis properties are shifted to the positive or negative side of a voltage axis. The hysteresis properties of a cell are almost symmetric with respect to an intersection point between the voltage axis (V) and polarization axis (P) immediately after data is written to the cell. As shown in FIG. 14, however, the hysteresis properties of a cell that is left unattended with data “1” written thereto are shifted in the direction of the arrow (toward the negative side of the voltage axis), or from the position defined by broken lines to that defined by solid lines. Similarly, as shown in FIG. 15, the hysteresis properties of a cell that is left unattended with data “0” written thereto are shifted in the direction of the arrow (toward the positive side of the voltage axis), or from the position defined by broken lines to that defined by solid lines.
Though the above imprint phenomenon occurs, the amount of signal (the amount of polarization) does not vary so greatly when data of a memory cell that is left unattended (hereinafter referred to as unattended data) is read out as it is, as shown in FIGS. 16 and 17. No problems occur in this case. When data that is rewritten with remanent polarization P whose direction is the same as that of remanent polarization of the unattended data, or data that is rewritten by the same data as the unattended data is read out, no problems occur in particular. If, however, the memory cells that cause the imprint phenomenon increase in number, data cannot be read correctly.
If unattended data, which is rewritten by data whose remanent polarization P is opposite in direction to that of the unattended data, is read out, the amount of remanent polarization reduces more than that in the normal case where no imprint phenomenon occurs. In other words, as shown in FIG. 18, data “0” whose remanent polarization P is opposite in direction to that of unattended data (data “1”) is written to a memory cell that is unattended with data “1” written thereto. Then, the amount of remanent polarization (black circle) of data “0” decreases more than that of the original remanent polarization (white circle) in the normal case by the shift of hysteresis properties. Thus, data “0” cannot be read correctly. Similarly, as shown in FIG. 19, data “1” whose remanent polarization P is opposite in direction to that of unattended data (data “0”) is written to a memory cell that is unattended with data “0” written thereto. Then, the amount of remanent polarization (black circle) of data “1” is reduced more than the original remanent polarization amount (white circle) in the normal case by the shift of hysteresis properties. Thus, data “1” cannot be read correctly.
As described above, the prior art FeRAM has the problem in which data cannot be read correctly when the number of memory cells that cause an imprint phenomenon and when unattended data is rewritten by data whose remanent polarization P is opposite in direction to that of the unattended data.